1. Field of the Invention
The present invention relates to an output circuit used in an integrated circuit (IC) device.
2. Description of the Related Art
In an IC device such as a aetal oxide semiconductor (MOS) device, a prior art output circuit is constructed by a P-channel MOS transistor connected between a power supply terminal and an output terminal and at least two N-channel MOS transistors connected between the output terminal and a ground terminal. The transistors are controlled by an input voltage. This will be explained later in detail.
In the above-described prior art output circuit, however, the power supply bounce and/or ground bounce is large. That is, when the input voltage is switched from high to low or vice versa, the output voltage at the output terminal is switched from low to high or vice versa. In such a transition state, the fall speed and rise speed of the output voltage depends upon not only the characteristics of the transistors, but also an external load connected to the output terminal. When the output voltage falls or rises, a current flows from the external load or into the external load, so that currents flowing through a power supply line and a ground line also change. This induces a power supply bounce or a ground bounce due to the inductance of the power supply line and the ground line. As a result, the noise phenomenon of the output voltage caused by the power supply bounce and the ground bounce generates error signals.
In order to suppress the power supply bounce and the ground bounce, one approach is to change the location of pins of the power supply line and the ground line and decrease the length of the pins, thus reducing the inductance of the power supply line and the ground line. However, in this case, if the number of loads connected to the IC device is increased due to the increase of number of data lines, and also the rate of clock signals is increased, the above-mentioned power supply bounce and ground bounce are remarkably increased.